The present invention relates to processes for creating holes in polymeric substrates and for fabricating a multi-layer electrical circuit assemblies.
Electrical components, for example, resistors, transistors, and capacitors, are commonly mounted on circuit panel structures such as printed circuit boards. Circuit panels ordinarily include a generally flat sheet of dielectric material with electrical conductors disposed on a major, flat surface of the sheet, or on both major surfaces. The conductors are commonly formed from metallic materials such as copper and serve to interconnect the electrical components mounted to the board. Where the conductors are disposed on both major surfaces of the panel, the panel may have via conductors extending through holes (or xe2x80x9cthrough viasxe2x80x9d) in the dielectric layer so as to interconnect the conductors on opposite surfaces. Multi-layer circuit panel assemblies have been made heretofore which incorporate multiple stacked circuit panels with additional layers of dielectric materials separating the conductors on mutually facing surfaces of adjacent panels in the stack. These multi-layer assemblies ordinarily incorporate interconnections extending between the conductors on the various circuit panels in the stack as necessary to provide the required electrical interconnections.
Polymeric films with pattened holes are useful in the manufacture of flexible circuits and various types of filters. Flexible circuits typically utilize unreinforced polymeric dielectric films on which to build circuitry levels. These circuits can conform to changing shapes and orientations by bending and twisting. The most common polymeric substrates used in flexible circuit assemblies are polyimide films such as KAPTON(trademark) (available from E.I. DuPont de Nemours and Company), and polyester films. In double-sided flexible circuits, it is desirable to have holes extending through the polymer film (hereafter referred to as xe2x80x9cthrough viasxe2x80x9d) through which electrical connections can be made between circuit patterns on opposing surfaces.
Through vias are typically fabricated by punching, etching, or photolithography of photosensitive polymers. Punching techniques have several drawbacks including possible deformation of the substrate, such as compression buckling or tearing. This technique is also unavailable to substrates that have additional layers thereon. Wet etching and plasma etching methods are commonly used to provide holes in polymeric substrates. Etching methods to date require careful selection of a limited number of resist chemistries and etchants to achieve selective removal of the desired polymeric material. Polyimide films are commonly etched by applying a concentrated basic solution, which can act on the substrate material by hydrolyzing the polymeric backbone.
U.S. Pat. No. 5,227,008 describes a method for making a flexible circuit using an aqueous processable photoresist. A fully cured polyimide film, one surface of which comprises a thin layer of copper, is laminated with a dry film photoresist. The photoresist is then exposed and developed. The exposed copper is plated to higher thickness, and the polyimide is etched with hot concentrated alkaline solution. The remaining resist is then removed with dilute basic solution to give a patterned substrate.
U.S. Pat. No. 3,833,436 describes a method for creating holes or through vias in a polyimide film. A resist is applied, exposed, developed and baked by standard methods, followed by immersion in hydrazine solution. Ultrasonic agitation is utilized to ensure adequate mixing of the etchant during the immersion step.
The above-mentioned art describes methods for creating holes or through vias that effectively depend on either mechanical means, or harsh conditions to chemically break down polymeric materials in the desired areas. As new dielectric materials are developed, new methods for handling and processing these materials are frequently necessary. In view of the prior art, there remains a need for processes that will create patterned holes in a variety of flexible polymeric substrates under mild conditions.
In one embodiment, the present invention is directed to a process for creating a via through a substrate. The process comprises the steps of (a) providing a substantially void-free film; (b) applying a resist onto the film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the film; and (e) removing the exposed areas of the film to form holes through the film.
In one embodiment, the present invention is directed to a process for creating a via through a cured substrate. The process comprises the steps of: (a) providing a substantially void-free curable film comprised of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition.
In another embodiment, the invention is directed toward a process for fabricating a multi-layer electrical circuit assembly comprising the steps of: (a) providing a substantially void-free curable film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition; (g) stripping the remaining resist; (h) applying a layer of metal to all surfaces; (i) applying a second resist over all surfaces of the layer of metal applied in step (h); (j) imaging and developing the second resist to reveal a predetermined pattern of uncovered underlying metal; (k) etching the uncovered portions of the underlying layer of metal; (l) stripping the remaining second resist to form an electrical circuit pattern; (m) applying a dielectric composition to all surfaces; (n) providing vias in the dielectric composition in predetermined locations; (o) applying a second layer of metal to all surfaces; (p) applying a third resist to all surfaces of the second layer of metal; (q) imaging and developing the third resist to expose a predetermined pattern of the second layer of metal; (r) etching the exposed portions of the second layer of metal to form an electrical circuit pattern; (s) stripping the remaining third resist; and (t) optionally repeating steps (m) through (s) one or more times to form multiple layers of interconnecting electrical circuit patterns.
The present invention is further directed to a substrate and circuit assembly prepared by the respective aforementioned processes.